Witam na mojej osobistej stronie WWW

dr Michał Tanaś

e-mail:

Michal.Tanas@amu.edu.pl

"Logic circuits design" 2024/2025

Dec 5th - test exam (repetition)
Dec 12th - first exam

Presentations

1. Introduction
2. Xilinx ISE - first simulation

Exercises

1. Basic logic gates
2. Combining logic gates into greater circuits
3. Interpretation of simulation results
4. Multiplexers
5. Demultiplexers
6. Repetition
7. Adders
8. Memory
9. Memory (part2)

Software

• Xilinx ISE

Building blocks

• 1-bit adder
• Combining adders